1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
A semiconductor device is provided with circuit elements such as a transistor, a resistance, a condenser and the like disposed on a semiconductor substrate, and the circuit elements are connected to one another via an interconnect for executing an instructed circuit operation, to thereby perform a function as required. The circuit elements have to be electrically insulated in order to effectively perform the circuit operation and function. Accordingly, various insulating and isolating techniques have been proposed, such as a trench isolation technique of filling a layer in a trench formed on a semiconductor substrate. A conventional example of a method of manufacturing a semiconductor device utilizing a trench isolation technique is described hereunder.
FIGS. 7A to 8C are schematic cross-sectional views showing a conventional method of manufacturing a semiconductor device.
Referring to FIG. 7A, a mask oxide layer 2 having an opening of 0.5 to 2 μm in width is formed in a thickness of 100 to 600 nm on a silicon substrate 1. Then an anisotropic etching is performed on the silicon substrate 1 utilizing the mask oxide layer 2 as an etching mask, so that a trench 3 of 1 to 5 μm in depth is formed on the silicon substrate 1. The trench 3 is to serve as an isolation trench.
Referring to FIG. 7B, the mask oxide layer 2 is removed, and a silicon oxide layer is formed in a thickness of 100 to 800 nm over a surface of the silicon substrate 1 and the trench 3 by a thermal oxidation process. This silicon oxide layer serves as a dielectric layer 4. Then a polycrystalline silicon layer is formed in a thickness of 150 to 1500 nm on the dielectric layer 4, for example by a CVD (Chemical Vapor Deposition) process, so that the trench 3 is filled with the polycrystalline silicon layer, to thereby constitute a trench isolation region 33. Here, the polycrystalline silicon layer that is filled in the trench 3 will be herein referred to as a filling polycrystalline silicon layer 5. Also, a layer formed by a CVD process will be herein referred to as a CVD layer.
Then as shown in FIG. 7C, an etch-back or a CMP (Chemical and Mechanical Polishing) process is performed so as to remove the filling polycrystalline silicon layer 5 except a portion formed in the trench isolation region 33.
Referring to FIG. 8A, a wet etching is performed so as to remove the dielectric layer 4 except a portion formed in the trench 3. Then as shown in FIG. 8B, a gate insulating layer 6 of a transistor is formed in a thickness of 3 to 30 nm on a surface of the silicon substrate 1 and the trench isolation region 33 by a CVD process, and a polycrystalline silicon layer is formed thereon in a thickness of 100 to 600 nm by a CVD process. In order to form a gate electrode, a conductive impurity is diffused in the polycrystalline silicon layer, so as to constitute an impurity-diffused polycrystalline silicon layer 7. Also, a resist defining a gate electrode pattern 14 is formed by a known lithography technique, after which an anisotropic etching is performed to form a gate electrode 8 constituted of the impurity-diffused polycrystalline silicon layer 7, and then the resist is removed as shown in FIG. 8C.
Also, JP-A Laid Open No. 2002-237518 and others disclose a method of reducing a recess formed in the trench isolation region.
With a conventional trench isolation technique, the etching for removing the dielectric layer 4 often overpasses a surface of the silicon substrate 1 and the filling polycrystalline silicon layer 5 in the wet etching performed in the process according to FIG. 8A. For this reason a gap A is prone to be formed between the dielectric layer 4 and the surface of the silicon substrate 1, and likewise a gap B is prone to be formed between the dielectric layer 4 and the filling polycrystalline silicon layer 5.
Accordingly, even though the gate insulating layer 6 is formed as described referring to FIG. 8B, the gate insulating layer 6 does not fill an entire portion of the trench between the gap A and the gap B, but instead forms a uniform layer along a shape of the gaps, thereby preserving a recessed shape of the trench. Therefore, though the anisotropic etching is performed to remove the impurity-diffused polycrystalline silicon layer 7, a sufficient etching effect cannot be achieved in the proximity of a bottom portion of the trench, which is coated with the gate insulating layer 6, and resultantly an etching residue 9 of the impurity-diffused polycrystalline silicon layer 7 often remains unremoved.
During a process from the etching for forming the gate electrode to the formation of an interlayer dielectric layer on the gate electrode, the etching residue 9 may be peeled off and freely float in a solution, for example in a cleaning process, to later stick to a surface of silicon substrate 1 as a waste. And such waste stuck to the surface of the silicon substrate 1 is prone to cause an abnormality in a characteristic of a semiconductor device, to thereby degrade reliability of the device. Also, a waste floating in a solution of a cleaning device may also stick to a surface of another silicon substrate, while the cleaning device is processing that silicon substrate. Further, the etching residue 9 may also freely float in the device because of a heat treatment, a CVD process or an ion implantation process, in addition to the cleaning process.
On the other hand, a technique disclosed in JP-A Laid Open No. 2002-237518 permits reducing a size of a recess formed in a trench isolation region, however cannot completely eliminate the recess, and therefore has not reached a solution of the problem of the waste from the etching residue. Besides, the problem of the waste from the etching residue may still be incurred even when the recess or the gap is very small.